Difference between revisions of "Resource:Seminar"

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{{SemNote
{{SemNote
|time='''2024-12-06 10:30-12:00'''
|time='''2026-04-10 10:30'''
|addr=4th Research Building A518
|addr=4th Research Building A518
|note=Useful links: [[Resource:Reading_List|📚 Readling list]]; [[Resource:Seminar_schedules|📆 Schedules]]; [[Resource:Previous_Seminars|🧐 Previous seminars]].
|note=Useful links: [[Resource:Reading_List|📚 Readling list]]; [[Resource:Seminar_schedules|📆 Schedules]]; [[Resource:Previous_Seminars|🧐 Previous seminars]].
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{{Latest_seminar
{{Latest_seminar
|abstract = Packet routing in virtual networks requires virtual-to-physical address translation. The address mappings are updated by a single party, i.e., the network administrator, but they are read by multiple devices across the network when routing tenant packets. Existing approaches face an inherent read-write performance tradeoff: they either store these mappings in dedicated gateways for fast updates at the cost of slower forwarding or replicate them at end-hosts and suffer from slow updates.SwitchV2P aims to escape this tradeoff by leveraging the network switches to transparently cache the address mappings while learning them from the traffic. SwitchV2P brings the mappings closer to the sender, thus reducing the first packet latency and translation overheads, while simultaneously enabling fast mapping updates, all without changing existing routing policies and deployed gateways. The topology-aware data-plane caching protocol allows the switches to transparently adapt to changing network conditions and varying in-switch memory capacity.Our evaluation shows the benefits of in-network address mapping, including an up to 7.8× and 4.3× reduction in FCT and first packet latency respectively, and a substantial reduction in translation gateway load. Additionally, SwitchV2P achieves up to a 1.9× reduction in bandwidth overheads and requires order-of-magnitude fewer gateways for equivalent performance.
|abstract = To effectively utilize heterogeneous specialized hardware units in modern GPUs, such as TensorCores and Tensor Memory Accelerators, this paper introduces PipeThreader, a new DNN compiler. PipeThreader proposes shifting scheduling functionality from hardware to software so as to enable more efficient and sophisticated computation pipelining with minimal manual effort. This is achieved through sTask-graph, a new DNN computation abstraction, a hierarchical hardware abstraction that captures the capabilities of specialized units, and new scheduling primitives. As a result, PipeThreader can discover efficient pipeline scheduling for well-studied DNN architectures like FlashAttention, achieving comparable or even superior performance. Additionally, it can uncover novel pipeline schemes for emerging models like Mamba2, delivering significantly better performance compared to state-of-the-art hand-crafted implementations. The code is open-sourced at https://github.com/tile-ai/tilelang.
|confname =SIGCOMM'24
|confname =OSDI'25
|link = https://dl.acm.org/doi/abs/10.1145/3651890.3672213
|link = https://www.usenix.org/conference/osdi25/presentation/cheng
|title= In-Network Address Caching for Virtual Networks
|title= PipeThreader: Software-defined pipelining for efficient DNN execution
|speaker=Dongting
|speaker=Junzhe
|date=2024-12-06
|date=2026-4-9
}}{{Latest_seminar
|abstract = Visible light communication (VLC) has become an important complementary means to electromagnetic communications due to its freedom from interference. However, existing Internet-of-Things (IoT) VLC links can reach only <10 meters, which has significantly limited the applications of VLC to the vast and diverse scenarios. In this paper, we propose ChirpVLC, a novel modulation method to prolong VLC distance from ≤10 meters to over 100 meters. The basic idea of ChirpVLC is to trade throughput for prolonged distance by exploiting Chirp Spread Spectrum (CSS) modulation. Specifically, 1) we modulate the luminous intensity as a sinusoidal waveform with a linearly varying frequency and design different spreading factors (SF) for different environmental conditions. 2) We design range adaptation scheme for luminance sensing range to help receivers achieve better signal-to-noise ratio (SNR). 3) ChirpVLC supports many-to-one and non-line-of-sight communications, breaking through the limitations of visible light communication. We implement ChirpVLC and conduct extensive real-world experiments. The results show that ChirpVLC can extend the transmission distance of 5W COTS LEDs to over 100 meters, and the distance/energy utility is increased by 532% compared to the existing work.
|confname = IDEA
|link = https://mobinets.cn/site/Resource:Seminar
|title= ChirpVLC：Extending The Distance of Low-cost Visible Light Communication with CSS Modulation
|speaker=Mengyu
|date=2024-12-06
}}
}}


{{Resource:Previous_Seminars}}
{{Resource:Previous_Seminars}}

Latest revision as of 10:37, 10 April 2026

Time: 2026-04-10 10:30
Address: 4th Research Building A518
Useful links: 📚 Readling list; 📆 Schedules; 🧐 Previous seminars.

Latest

  1. [OSDI'25] PipeThreader: Software-defined pipelining for efficient DNN execution, Junzhe
    Abstract: To effectively utilize heterogeneous specialized hardware units in modern GPUs, such as TensorCores and Tensor Memory Accelerators, this paper introduces PipeThreader, a new DNN compiler. PipeThreader proposes shifting scheduling functionality from hardware to software so as to enable more efficient and sophisticated computation pipelining with minimal manual effort. This is achieved through sTask-graph, a new DNN computation abstraction, a hierarchical hardware abstraction that captures the capabilities of specialized units, and new scheduling primitives. As a result, PipeThreader can discover efficient pipeline scheduling for well-studied DNN architectures like FlashAttention, achieving comparable or even superior performance. Additionally, it can uncover novel pipeline schemes for emerging models like Mamba2, delivering significantly better performance compared to state-of-the-art hand-crafted implementations. The code is open-sourced at https://github.com/tile-ai/tilelang.

History

2024

2023

2022

2021

2020

  • [Topic] [ The path planning algorithm for multiple mobile edge servers in EdgeGO], Rong Cong, 2020-11-18

2019

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2017

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