Difference between revisions of "Resource:Seminar"

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{{SemNote
{{SemNote
|time='''2025-06-06 10:30-12:00'''
|time='''2026-04-10 10:30'''
|addr=4th Research Building A518
|addr=4th Research Building A518
|note=Useful links: [[Resource:Reading_List|📚 Readling list]]; [[Resource:Seminar_schedules|📆 Schedules]]; [[Resource:Previous_Seminars|🧐 Previous seminars]].
|note=Useful links: [[Resource:Reading_List|📚 Readling list]]; [[Resource:Seminar_schedules|📆 Schedules]]; [[Resource:Previous_Seminars|🧐 Previous seminars]].
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{{Latest_seminar
{{Latest_seminar
|abstract = Unlike traditional data collection applications (e.g., environment monitoring) that are dominated by uplink transmissions, the newly emerging applications (e.g., device actuation, firmware update, packet reception acknowledgement) also pose ever-increasing demands on downlink transmission capabilities. However, current LoRaWAN falls short in supporting such applications primarily due to downlink-uplink asymmetry. While the uplink can concurrently receive multiple packets, downlink transmission is limited to a single logical channel at a time, which fundamentally hinders the deployment of downlink-hungry applications. To tackle this practical challenge, FDLoRa develops the first-of-its-kind in-band full-duplex LoRa gateway design with novel solutions to mitigate the impact of self-interference (i.e., strong downlink interference to ultra-weak uplink reception), which unleashes the full spectrum for in-band downlink transmissions without compromising the reception of weak uplink packets. Built upon the full-duplex gateways, FDLoRa introduces a new downlink framework to support concurrent downlink transmissions over multiple logical channels of available gateways. Evaluation results demonstrate that FDLoRa boosts downlink capacity by 5.7x compared to LoRaWAN on a three-gateway testbed and achieves 2.58x higher downlink concurrency per gateway than the state-of-the-art.
|abstract = To effectively utilize heterogeneous specialized hardware units in modern GPUs, such as TensorCores and Tensor Memory Accelerators, this paper introduces PipeThreader, a new DNN compiler. PipeThreader proposes shifting scheduling functionality from hardware to software so as to enable more efficient and sophisticated computation pipelining with minimal manual effort. This is achieved through sTask-graph, a new DNN computation abstraction, a hierarchical hardware abstraction that captures the capabilities of specialized units, and new scheduling primitives. As a result, PipeThreader can discover efficient pipeline scheduling for well-studied DNN architectures like FlashAttention, achieving comparable or even superior performance. Additionally, it can uncover novel pipeline schemes for emerging models like Mamba2, delivering significantly better performance compared to state-of-the-art hand-crafted implementations. The code is open-sourced at https://github.com/tile-ai/tilelang.
|confname = SenSys'24
|confname =OSDI'25
|link = https://dl.acm.org/doi/10.1145/3666025.3699338
|link = https://www.usenix.org/conference/osdi25/presentation/cheng
|title= FDLoRa: Tackling Downlink-Uplink Asymmetry with Full-duplex LoRa Gateways
|title= PipeThreader: Software-defined pipelining for efficient DNN execution
|speaker= Chenkai
|speaker=Junzhe
|date=2025-05-23
|date=2026-4-9
}}
{{Latest_seminar
|abstract = Deploying deep convolutional neural networks (CNNs) for edge-based video analytics poses significant challenges due to the intensive computing demands. Model partitioning has emerged as a promising solution by offloading segments of CNNs to multiple proximal edge devices for collaborative inference. However, this approach often incurs substantial cross-device transmission overhead, particularly in handling intermediate feature maps. To address these limitations, we propose ReDream (REsidual feature-DRivEn mixed spArse coding for Model partitioning), a novel edge-centric video analytics framework that jointly optimizes  transmission efficiency and inference accuracy. ReDream introduces two key innovations: 1) It enhances the sparsity of intermediate features by replacing activation functions with ReLU in selected CNN layers and retraining, thereby increasing the proportion of zero-valued elements. 2) It leverages the heterogeneous distribution of feature data across layers by applying a mixed sparse coding scheme, i.e., selecting different compression methods adaptively to optimize model partitioning. These optimizations enable ReDream to support more efficient cross-device inference while maintaining high model accuracy, making it well-suited for real-time deployment in collaborative edge environments.
|confname = IDEA
|link = https://mns.uestc.cn/wiki/Research:InProgress/MixedSparseCoding
|title= ReDream: Residual Feature-Driven Mixed Sparse Coding for Model Partitioning
|speaker=Xianyang
|date=2025-05-23
}}
}}


{{Resource:Previous_Seminars}}
{{Resource:Previous_Seminars}}

Latest revision as of 10:37, 10 April 2026

Time: 2026-04-10 10:30
Address: 4th Research Building A518
Useful links: 📚 Readling list; 📆 Schedules; 🧐 Previous seminars.

Latest

  1. [OSDI'25] PipeThreader: Software-defined pipelining for efficient DNN execution, Junzhe
    Abstract: To effectively utilize heterogeneous specialized hardware units in modern GPUs, such as TensorCores and Tensor Memory Accelerators, this paper introduces PipeThreader, a new DNN compiler. PipeThreader proposes shifting scheduling functionality from hardware to software so as to enable more efficient and sophisticated computation pipelining with minimal manual effort. This is achieved through sTask-graph, a new DNN computation abstraction, a hierarchical hardware abstraction that captures the capabilities of specialized units, and new scheduling primitives. As a result, PipeThreader can discover efficient pipeline scheduling for well-studied DNN architectures like FlashAttention, achieving comparable or even superior performance. Additionally, it can uncover novel pipeline schemes for emerging models like Mamba2, delivering significantly better performance compared to state-of-the-art hand-crafted implementations. The code is open-sourced at https://github.com/tile-ai/tilelang.

History

2024

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2020

  • [Topic] [ The path planning algorithm for multiple mobile edge servers in EdgeGO], Rong Cong, 2020-11-18

2019

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